Multi-cell structure for non-volatile resistive memory

ABSTRACT

A non-volatile memory comprises an array of a plurality of non-volatile memory cells, a controller coupled to the array, and an evaluator coupled to an output of the array. In a first operational mode, the controller receives a logical address and selects one non-volatile memory cell for access. In a second operational mode, and the controller receives a logical address and selects N non-volatile memory cells for access in which N is an integer greater than 1. If the logical address is for a read access, in the first operational mode the evaluator is disabled and the read-address output of the array corresponds to one selected non-volatile memory cell, and in the second operational mode the evaluator determines an read-address output corresponding to the received logical address based on a read output of the N selected non-volatile memory cells.

CROSS-REFERENCE TO RELATED APPLICATION

This patent application claims the priority benefit under 35 U.S.C.§119(e) of U.S. Provisional Patent Application No. 62/298,984 filed onFeb. 23, 2016, the disclosure of which is incorporated herein byreference in its entirety.

TECHNICAL FIELD

The present disclosure relates to non-volatile memories. Moreparticularly, the present disclosure relates resistive random accessmemory (ReRAM) devices.

BACKGROUND

Resistive memory, such as ReRAM and memristors, shows great potential asa future non-volatile memory technology because resistive memoryprovides high endurance characteristics, has high density, has3D-stacking capability, has cross-point architecture, requires norefresh overhead (as is necessary with dynamic random access memory(DRAM)), and has no resistance-drift problem as experienced withphase-change memory (PCM).

Process variability may become a critical issue because aggressivescaling of resistive memory technologies may result in device parameterfluctuations and, consequently, adversely affect the performance and thereliability of resistive memory devices. For example, one deviceparameter that may be adversely affected by process variability is thatReRAM devices exhibit lognormal switching time behavior, and maintainingcell-level reliability may involve relatively long write latency andrelatively high write energy.

SUMMARY

An exemplary embodiment provides a non-volatile memory comprising: anarray of non-volatile memory cells; a controller coupled to the array inwhich the controller is to receive in a first operational mode a readaddress and to select one non-volatile memory cell for read access, andthe controller is to receive in a second operational mode a read addressand to select N non-volatile memory cells for read access in which N isan integer greater than 1; and an evaluator coupled to an output of thearray in which in the first operational mode the evaluator is to bedisabled and the read-address output of the array corresponds to thereceived address based on the read output of the one selectednon-volatile memory cell, and in the second operational mode theevaluator is to determine an read-address output corresponding to thereceived address based on a read output of the N selected non-volatilememory cells. In one embodiment, the controller may include a mappingtable that identifies the N non-volatile memory cells corresponding tothe received address signal. In another embodiment, the controller is tofurther receive in the first operational mode a write address signal andto select one non-volatile memory cell for write access, and thecontroller is to further receive in the second operational mode a writeaddress signal and to select N non-volatile memory cells for writeaccess.

Another exemplary embodiment provides a non-volatile memory comprising:an array of non-volatile memory cells; and a controller coupled to thearray in which the controller comprises a logical address register and amapping table in which the logical address register is to receive alogical read address and the controller in a first operational mode tocontrol the mapping table is to map the received logical read address toone physical address of a non-volatile memory cell for read access, andthe controller in a second operational mode is to control the mappingtable to map the received logical read address to N physical addressesof N non-volatile memory cells for read access in which N is an integergreater than 1. In one embodiment, the non-volatile memory may comprisean evaluator coupled to an output of the array of non-volatile memorycells in which in the first operational mode the evaluator is to bedisabled and a read output of the array of non-volatile memory cellscorresponds to the received logical read address, and in the secondoperational mode the evaluator is to determine an read outputcorresponding to the received address signal based on a read output ofthe N non-volatile memory cells. In one embodiment, the logical addressregister is to further receive a logical write address, and thecontroller in the first operational mode is to further control themapping table to map the received logical write address to onenon-volatile memory cell for write access, and the controller in thesecond operational mode is to control the mapping table to map thereceived logical write address to N physical addresses of N non-volatilememory cells for write access.

Yet another exemplary embodiment provides a controller for anon-volatile memory comprising: a logical address register to receive alogical read address for an array of non-volatile memory cells; and amapping table coupled to the logical address register in which themapping table in a first operational mode is to map the received logicalread address to a physical address of one non-volatile memory cell of anarray of non-volatile memory cells for read access, and in a secondoperational mode is to map the received logical read address to Nphysical addresses of N non-volatile memory cells of the array ofnon-volatile memory cells for read access in which N is an integergreater than 1. In one embodiment, the logical address register is tofurther receive a logical write address, and in the first operationalmode the mapping table is to further map the received logical writeaddress to one non-volatile memory cell for write access, and in thesecond operational mode the mapping table is to further map the receivedlogical write address to N physical addresses of N non-volatile memorycells for write access.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following section, the aspects of the subject matter disclosedherein will be described with reference to exemplary embodimentsillustrated in the figures, in which:

FIG. 1 depicts an example functional block diagram of a multi-cellresistive memory system according to the subject matter disclosedherein;

FIG. 2 shows a graph of a switching probability as a function ofnormalized write latency of the resistive memory cell;

FIG. 3 depicts a flow diagram of a process of configuring and operatinga multi-cell resistive system, such as the multi-cell resistive memorysystem of FIG. 1, in accordance with the subject matter disclosedherein;

FIG. 4 depicts an electronic device that includes a multi-cell resistivesystem according to the subject matter disclosed herein; and

FIG. 5 depicts a memory system that may comprise a multi-cell resistivememory system according to the subject matter disclosed herein.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are setforth in order to provide a thorough understanding of the disclosure. Itwill be understood, however, by those skilled in the art that thedisclosed aspects may be practiced without these specific details. Inother instances, well-known methods, procedures, components and circuitshave not been described in detail not to obscure the subject matterdisclosed herein.

Reference throughout this specification to “one embodiment” or “anembodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment disclosed herein. Thus, the appearances ofthe phrases “in one embodiment” or “in an embodiment” or “according toone embodiment” (or other phrases having similar import) in variousplaces throughout this specification are not necessarily all referringto the same embodiment. As used herein, the word “exemplary” means“serving as an example, instance, or illustration.” Any embodimentdescribed herein as “exemplary” is not to be construed as necessarilypreferred or advantageous over other embodiments. Furthermore, theparticular features, structures, or characteristics may be combined inany suitable manner in one or more embodiments. Also, depending on thecontext of discussion herein, a singular term may include thecorresponding plural forms and a plural term may include thecorresponding singular form. It is further noted that various figures(including component diagrams) shown and discussed herein are forillustrative purpose only, and are not drawn to scale. Similarly,various waveforms and timing diagrams are shown for illustrative purposeonly.

The terms “first,” “second,” etc., as used herein, are used as labelsfor nouns that they precede, and do not imply any type of ordering(e.g., spatial, temporal, logical, etc.) unless explicitly defined assuch. Furthermore, the same reference numerals may be used across two ormore figures to refer to parts, components, blocks, circuits, units, ormodules having the same or similar functionality. Such usage is,however, for simplicity of illustration and ease of discussion only; itdoes not imply that the construction or architectural details of suchcomponents or units are the same across all embodiments or suchcommonly-referenced parts/modules are the only way to implement theteachings of particular embodiments disclosed herein.

Embodiments disclosed herein provide a multi-cell, non-volatileresistive memory structure that is capable of selectively providing ahigh memory capacity (size) or, alternatively, a high memory-cellreliability. That is, embodiments provide a multi-cell, non-volatileresistive memory comprising a first operation mode that provides anincreased memory capacity and a second operating mode that provides anincreased memory-cell reliability. It should be understood that althoughthe overall physical memory size of a non-volatile resistive memoryarray may be fixed, the phrases “high memory capacity,” “increasedmemory capacity,” and other similar phrases as used herein mean a memorysize that may be up to and include the overall physical memory size ofthe array. In the same vein, the phrase “reduced memory capacity” andother similar phrases as used herein mean a memory size that is lessthan the overall physical memory size of the array.

Embodiments disclosed herein also include an evaluation mechanism thatis disabled in the first operational mode and is enabled in the secondoperational mode. If evaluation mechanism is disabled, read accesses tothe multi-cell, non-volatile resistive memory are based on accessing asingle physical memory address. If the evaluation mechanism is enabled,read accesses to the multi-cell, non-volatile resistive memory are basedon accessing N physical memory addresses in which N is an integergreater than 1. Thus, embodiments disclosed herein provide anon-volatile resistive memory having a selectable operational mode thatprovides either a higher-speed, higher energy-consumption mode with areduced memory capacity or, alternatively, a slower-speed, highermemory-cell reliability mode with an increased memory capacity.

FIG. 1 depicts an example functional block diagram of a multi-cellresistive memory system 100 according to the subject matter disclosedherein. System 100 includes a controller unit 101, a non-volatile memoryarray 102, an interface unit 103, an evaluation unit 104, and a cache105. System 100 may be coupled to an address bus 106 and a data bus 107of, for example, a host system (not shown), through the interface unit103. In one embodiment, the non-volatile memory array 102 may comprisean array of resistive memory cells and/or an array of memristors. In oneembodiment, system 100 may be embodied as a solid-state drive (SSD). Inanother embodiment, system 100 may be embodied as a main system memory.

In one embodiment, controller unit 101 may receive address and controldata information from the address bus 106 and/or data bus 107. In oneembodiment, controller unit 101 may comprise registers (not shown) thatare used to set an operational mode by being addressed. In anotherembodiment, controller unit 101 may comprise registers (not shown) thatset an operation mode based on a received address and correspondinglyreceived data. In one embodiment, controller unit 101 may receivecontrol information that is used to control the operational mode ofnon-volatile memory array 102 and evaluation unit 104.

In one embodiment, the resistive memory cells of the non-volatile memoryarray 102 may be configured in a well-known arrangement of sectorsand/or pages, and may be configured to have a plurality of memory cellsorganized in a word arrangement of any number of bits (i.e., a multi-bitword). Although the resistive memory cells of the non-volatile memoryarray 102 may be configured in a well-known arrangement of sectorsand/or pages and/or bits, the following description of the subjectmatter disclosed herein will focus on single memory cells. It should beunderstood that the subject matter disclosed herein is equallyapplicable to multi-bit words.

In one embodiment, the non-volatile memory array 102 comprises an arrayof resistive memory cells that are arranged in one or more rows (notshown) and one or more columns (not shown). As mentioned, in oneembodiment, at least one memory cell of array 102 may be a resistivememory cell. In another embodiment, at least one memory cell of array102 may be a memristor. Memory cells, such resistive memory devicesexhibit a lognormal switching-time characteristic, as disclosed by G.Medeiro-Ribeiro et al., Lognormal switching times for titanium dioxidebipolar memristors: origin and resolution, Nanotechnology, IOPPublishing, 22 (2011) 095702. In one embodiment, the non-volatile memoryarray 102 comprises an array of memory cells that exhibit lognormalswitching-time characteristics.

FIG. 2 shows a graph 200 of a switching probability as a function ofnormalized write latency of the resistive memory cell. FIG. 2 shows thelognormal switching time characteristic of a resistive memory cell. Asshown in FIG. 2, to increase the probability that a resistive memorycell will record a write operation, that is, record a change (or aswitch) of the datum stored in the resistive memory cell, the write time(and write energy) should correspondingly increase. Conversely, areduced write latency (and a reduced write energy) corresponds to adecreased switching probability for a resistive memory cell. Table 1below sets forth some example normalized write latencies forcorresponding a BER for a resistive memory cell.

TABLE 1 Normalized Write Latency (twr) Bit Error Rate (BER) 403 <10⁻⁹274 <10⁻⁸ 181 <10⁻⁷ 116 <10⁻⁶ 71 <10⁻⁵

In one embodiment, system 100 may be configured to utilize the lognormalwrite latency characteristic of a resistive memory cell to provide amulti-cell, non-volatile resistive memory that is capable of selectivelyproviding a desired memory capacity (size), or a desired level ofmemory-cell reliability (i.e., a desired BER). In another embodiment,system 100 may be configured to utilize the lognormal write latencycharacteristics of a resistive memory cell to provide a multi-cell,non-volatile resistive memory that is capable of providing a desired lowwrite latency or, a desired lower memory capacity.

Returning to FIG. 1, the controller unit 101 may include a controllerlogic 110, a mode register 111, a mapping table 112 and a logicaladdress register 113. The mode register 111 may receive controlinformation that sets either a first operational mode or a secondoperational mode. The first operational mode may provide an increasedmemory capacity (size), whereas the second operating mode may provide anincreased memory-cell reliability and/or a decreased write latency. Themapping table 112 may include a plurality of entries for logicaladdresses that are used by the system 100, and a plurality of entriesfor physical addresses of the non-volatile memory array 102 thatcorrespond to logical addresses. The logical address register 113 mayreceive a logical address that is input to the mapping table 112. Themapping table may output one or more physical addresses that correspondsto the logical address output from the logical address register.

In the first operational mode, the mapping table 112 may be configuredto associate a single logical address to a single physical address, thatis, a one-to-one logical-to-physical address association. Additionally,the evaluation unit 104 may be disabled, or bypassed. A single logicaladdress may be mapped to a single physical address in the non-volatilememory array 102 through row and column selectors (not shown). Althoughmapping table 112 is depicted in FIG. 1 as mapping a single logicaladdress into multiple physical addresses, it should be understood thatin the first operating mode a single logical address (LSA) is mappedinto only one physical address (DSA1 or DSA2 or DSA3). The datum storedin the memory cell at the physical address corresponding to a receivedlogical address is output and stored in cache 105, which may be dynamicrandom access memory or static random access memory, for subsequentoutput to the data bus 107.

In the second operational mode, the mapping table 112 may be configuredto associate a single logical address to a plurality of physicaladdresses, that is, a one-to-many logical-to-physical addressassociation. In the second operational mode, the evaluation unit 104 maybe enabled. A single logical address may be mapped to multiple physicaladdresses in the non-volatile memory array 102. As depicted in FIG. 1,the mapping table 112 maps a single logical address (LSA) into multiplephysical addresses (DSA1, DSA1 and DSA3) The outputs of the memory cellsat the multiple physical addresses corresponding to a received logicaladdress are evaluated by the evaluation unit 104. The output of theevaluation unit 104 is stored in cache 105 for subsequent output to thedata bus 107.

The evaluation unit 104 outputs a value that corresponds to the combinedoutputs of the memory cells corresponding to the multiple physicaladdresses. In one embodiment, the evaluation unit 104 may generate anoutput based on a well-known voting-evaluation technique. In anotherembodiment, the evaluation unit 104 may generate an output based amajority-detection technique, that is, the output of the evaluation unit104 is based on the outputs of the multiple memory cells that is in themajority.

The number of physical addresses that a logical address is mapped intoin the second operational mode may be a function of a desired level ofmemory-cell reliability for the non-volatile memory array 102 (i.e., anobserved BER for the non-volatile memory array 102). According to thesubject matter disclosed herein, multiple resistive memory cells of thenon-volatile memory array 102 could be simultaneously written at a lowerwrite latency (and correspondingly lower energy level) to store the samedatum. For example, consider a resistive memory array in which thedesired bit error rate (BER) is 10⁻⁹ for the array. To achieve thislevel of BER, the normalized write latency for a single resistive memorycell may be approximately 403. If three resistive memory cells are usedto simultaneously store the same datum at the same BER of 10⁻⁹, thenormalized write latency may be reduced to approximately 62. Anormalized write latency of 62 may result in a BER of 1.8×10⁻⁵ on anindividual memory cell basis, but because three memory cells are storingthe same datum, the overall BER is improved to 10⁻⁹ (that is, theobserved BER of 10⁻⁹).

In one embodiment, a rough estimate of the energy savings for theexample of using three resistive memory cells to achieve a BER of 10⁻⁹for a normalized write latency of 62 is that about three times (3×) lessenergy is used than using a single memory cell to achieve a BER of 10⁻⁹for a normalized write latency of 403. More specifically,

E=VIt,   (1)

in which E is the energy in Joules, V is the voltage in Volts, I is thecurrent in Amperes, and t is the time in seconds. If the voltage V andthe current I are considered to be fixed, the write latency for a singlememory cell has been reduced about a factor of 6, but because threememory cells are being used, the energy is reduced by about a factor of2.

In one embodiment, the mode register 111 may be configured to generallyselect N memory cells in which N is an integer greater than 1. Themapping table would be similarly configured to associate a singlelogical address to N of physical addresses, that is, a 1-to-Nlogical-to-physical address association, and the evaluation unit 104would be configured to evaluate the outputs of N memory cells.

Thus, in the second operational mode, the write latency (andcorresponding write energy) may be reduced while still maintaining arelatively high BER on an individual resistive memory cell basis. Thereduced write latency is obtained by trading memory capacity for thereduced write latency. The observed BER may be further increased (orimproved) with correspondingly reduced write latency by using additionalmemory cells to store the same datum, but by correspondingly decreasingthe memory capacity of the non-volatile memory array.

FIG. 3 depicts a flow diagram 300 of a process of configuring andoperating a multi-cell resistive system, such as the multi-cellresistive memory system 100 of FIG. 1, in accordance with the subjectmatter disclosed herein. Referring to FIGS. 1 and 3, at operation 301,the process starts during an initialization mode of the multi-cellresistive memory system, such as when the multi-cell resistive memorysystem is being formated. In one embodiment, the multi-cell resistivememory system 100 can only change the operational mode during aformatting operation and cannot change the operational mode duringruntime. If the non-volatile memory array 102 is reformated, flow wouldbegin again at operation 301. At operation 302, the particular mode ofoperation is received by the mode register 111. At operation 303, it isdetermined in a well-known manner whether the received mode of operationis the first operational mode or the second operational mode.

If, at operation 303, the received mode of operation is determined to bethe first operational mode, flow continues to operation 304 where themode register 111 configures the mapping table 112 to associate a singlelogical address to a single physical address (1-to-1) and the evaluationunit 104 is disabled, or bypassed. In one embodiment, the controllerlogic 110 reads the mode register 111 and based on the contents of themode register 111, configures the mapping table 112 to associate asingle logical address to a single physical address (1-to-1) and theevaluation unit 104 is disabled, or bypassed. In another embodiment, themode register 111 includes one or more outputs that configure themapping table 112 to associate a single logical address to a singlephysical address (1-to-1) and the evaluation unit 104 is disabled, orbypassed. At operation 305, a logical address is received by the logicaladdress register 113. At operation 306, it is determined in a well-knownmanner whether the received logical address is for a read access or awrite access. If the received logical address is determined to be for awrite access, the mapping table 112 maps logical address to a physicaladdress at operation 307, and at operation 308, the datum is written tothe physical address. Flow returns to operation 305. If, at operation306, it is determined that the received logical addresss is determinedto be for a read access, the mapping table 112 maps the logical addressto a physical address at operation 309, and at operation 310, the datumassociated with the accessed physical address is output to the cache105. Flow returns to operation 305. mapping table 112 maps the logicaladdress to a physical address, and the physical address is accessed.

If, at operation 303, the received mode of operation is determined to bethe second operational mode, flow continues to operation 311 where themode register 111 configures the mapping table 112 to associate a singlelogical address to a plurality of physical addresses (1-to-N in which Nis an integer greater than 1) and the evaluation unit 104 is enabled. Inone embodiment, the controller logic 110 reads the mode register 111 andbased on the contents of the mode register 111, configures the mappingtable 112 to associate a single logical address to a N physicaladdresses (1-to-N) and the evaluation unit 104 is enabled. In anotherembodiment, the mode register 111 includes one or more outputs thatconfigure the mapping table 112 to associate a single logical address toa N physical address (1-to-N) and the evaluation unit 104 is enabled. Atoperation 312, a logical address is received by the logical addressregister 113. At operation 313, it is determined in a well-known mannerwhether the received logical address is for a read access or a writeaccess. If the received logical address is determined to be for a writeaccess, the mapping table 112 maps logical address to N physicaladdresses at operation 314, and at operation 315, the datum is writtento the N physical addresses. Flow returns to operation 312. If, atoperation 313, it is determined that the received logical addresss isdetermined to be for a read access, the mapping table 112 maps thelogical address to N physical addresses at operation 316. At operation317, the evaluation unit 104 evaluates the outputs of the accessed Nphysical addresses. At operation 317, the evaluation unit 104 outputsthe evaluated output to the cache 105. Flow returns to operation 312.

FIG. 4 depicts an electronic device 400 that includes a multi-cellresistive system according to the subject matter disclosed herein.Electronic device 400 may be used in, but not limited to, a computingdevice, a personal digital assistant (PDA), a laptop computer, a mobilecomputer, a web tablet, a wireless phone, a cell phone, a smart phone, adigital music player, or a wireline or wireless electronic device. Theelectronic device 400 may comprise a controller 410, an input/outputdevice 420 such as, but not limited to, a keypad, a keyboard, a display,or a touch-screen display, a memory 430, and a wireless interface 440that are coupled to each other through a bus 450. In one embodiment, theinput/output device 420 may include a multi-cell non-volatile resistivememory system according to the subject matter disclosed herein. In oneembodiment, memory 430 may include a multi-cell non-volatile resistivememory system according to the subject matter disclosed herein. Thecontroller 410 may comprise, for example, at least one microprocessor,at least one digital signal process, at least one microcontroller, orthe like. The memory 430 may be configured to store a command code to beused by the controller 410 or a user data. The electronic device 400 mayuse a wireless interface 440 configured to transmit data to or receivedata from a wireless communication network using a RF signal. Thewireless interface 440 may include, for example, an antenna, a wirelesstransceiver and so on. The electronic system 400 may be used in acommunication interface protocol of a communication system, such as, butnot limited to, Code Division Multiple Access (CDMA), Global System forMobile Communications (GSM), North American Digital Communications(NADC), Extended Time Division Multiple Access (E-TDMA), Wideband CDMA(WCDMA), CDMA2000, Wi-Fi, Municipal Wi-Fi (Muni Wi-Fi), Bluetooth,Digital Enhanced Cordless Telecommunications (DECT), Wireless UniversalSerial Bus (Wireless USB), Fast low-latency access with seamless handoffOrthogonal Frequency Division Multiplexing (Flash-OFDM), IEEE 802.20,General Packet Radio Service (GPRS), iBurst, Wireless Broadband (WiBro),WiMAX, WiMAX-Advanced, Universal Mobile Telecommunication Service-TimeDivision Duplex (UMTS-TDD), High Speed Packet Access (HSPA), EvolutionData Optimized (EVDO), Long Term Evolution-Advanced (LTE-Advanced),Multichannel Multipoint Distribution Service (MMDS), and so forth.

FIG. 5 depicts a memory system 500 that may comprise a multi-cellresistive memory system according to the subject matter disclosedherein. The memory system 500 may comprise a memory device 510 forstoring large amounts of data and a memory controller 520. In oneembodiment, the memory device 510 may comprise an array of resistivememory cells. The memory controller 520 controls the memory device 510to read data stored in the memory device 510 or to write data into thememory device 510 in response to a read/write request of a host 530. Thememory controller 520 may include an address-mapping table for mapping alogical address provided from the host 520 (e.g., a mobile device or acomputer system) into one or more physical addresses of the memorydevice 510 according to the subject matter disclosed herein.

As will be recognized by those skilled in the art, the innovativeconcepts described herein can be modified and varied over a wide rangeof applications. Accordingly, the scope of claimed subject matter shouldnot be limited to any of the specific exemplary teachings discussedabove, but is instead defined by the following claims.

What is claimed is:
 1. A non-volatile memory, comprising: an array ofnon-volatile memory cells; a controller coupled to the array, thecontroller to receive in a first operational mode a read address and toselect one non-volatile memory cell for read access, and the controllerto receive in a second operational mode a read address and to select Nnon-volatile memory cells for read access in which N is an integergreater than 1; and an evaluator coupled to an output of the array, inthe first operational mode the evaluator to be unused and theread-address output of the array corresponds to the received addressbased on the read output of the one selected non-volatile memory cell,and in the second operational mode the evaluator is used to determine anread-address output corresponding to the received address based on aread output of the N selected non-volatile memory cells.
 2. Thenon-volatile memory according to claim 1, wherein the controllerincludes a mapping table that identifies the N non-volatile memory cellscorresponding to the received address signal.
 3. The non-volatile memoryaccording to claim 2, wherein the controller is to further receive inthe first operational mode a write address signal and to select onenon-volatile memory cell for write access, and the controller is tofurther receive in the second operational mode a write address signaland to select N non-volatile memory cells for write access.
 4. Thenon-volatile memory according to claim 1, wherein at least onenon-volatile memory cell comprises a resistive random access memory(ReRAM) cell.
 5. The non-volatile memory according to claim 1, whereinat least one non-volatile memory cell comprises a memristor.
 6. Thenon-volatile memory according to claim 1, wherein the non-volatilememory comprises a solid-state drive (SSD) or a main memory.
 7. Thenon-volatile memory according to claim 1, wherein the first operationalmode comprises a slow, high-power mode.
 8. The non-volatile memoryaccording to claim 1, wherein the second operational mode comprises afast, low-power mode.
 9. The non-volatile memory array according toclaim 1, wherein N =3.
 10. A non-volatile memory, comprising: an arrayof non-volatile memory cells; and a controller coupled to the array, thecontroller comprising a logical address register and a mapping table,the logical address register to receive a logical read address and thecontroller in a first operational mode to control the mapping table tomap the received logical read address to one physical address of anon-volatile memory cell for read access, and the controller in a secondoperational mode to control the mapping table to map the receivedlogical read address to N physical addresses of N non-volatile memorycells for read access in which N is an integer greater than
 1. 11. Thenon-volatile memory according to claim 10, further comprising anevaluator coupled to an output of the array of non-volatile memorycells, in the first operational mode the evaluator is to be unused and aread output of the array of non-volatile memory cells corresponds to thereceived logical read address, and in the second operational mode theevaluator is used to determine an read output corresponding to thereceived address signal based on a read output of the N non-volatilememory cells.
 12. The non-volatile memory according to claim 10, whereinthe logical address register is to further receive a logical writeaddress, and wherein the controller in the first operational mode tofurther control the mapping table to map the received logical writeaddress to one non-volatile memory cell for write access, and thecontroller in the second operational mode to control the mapping tableto map the received logical write address to N physical addresses of Nnon-volatile memory cells for write access.
 13. The non-volatile memoryaccording to claim 10 wherein at least one non-volatile memory cellcomprises a resistive random access memory (ReRAM) cell or a memristor.14. The non-volatile memory according to claim 10, wherein thenon-volatile memory comprises a solid-state drive (SSD) or a mainmemory.
 15. The non-volatile memory according to claim 10, wherein thefirst operational mode comprises a slow, high-power mode, and whereinthe second operational mode comprises a fast, low-power mode.
 16. Thenon-volatile memory array according to claim 1, wherein N=3.
 17. Acontroller for a non-volatile memory, comprising: a logical addressregister to receive a logical read address for an array of non-volatilememory cells; and a mapping table coupled to the logical addressregister, the mapping table in a first operational mode to map thereceived logical read address to a physical address of one non-volatilememory cell of an array of non-volatile memory cells for read access,and in a second operational mode to map the received logical readaddress to N physical addresses of N non-volatile memory cells of thearray of non-volatile memory cells for read access in which N is aninteger greater than
 1. 18. The controller according to claim 17,wherein the logical address register is to further receive a logicalwrite address, and wherein in the first operational mode the mappingtable to further map the received logical write address to onenon-volatile memory cell for write access, and in the second operationalmode the mapping table to further map the received logical write addressto N physical addresses of N non-volatile memory cells for write access.19. The controller according to claim 18, wherein N=3.
 20. Thecontroller according to claim 18, wherein the array of non-volatilememory cells comprises at least one resistive random access memory(ReRAM) cell or at least one memristor.